Just to be clear, artemonster isn't talking about using an FPGA. Verilator is software that complies Verilog to C++, so you'd still end up with a software emulator.
The upside to this is that Verilog makes it very easy to model parallel hardware. The downside is that you have to model the hardware at the clock-cycle, "flip-flops and Boolean logic" level of detail.
The upside to this is that Verilog makes it very easy to model parallel hardware. The downside is that you have to model the hardware at the clock-cycle, "flip-flops and Boolean logic" level of detail.